The present invention relates to a semiconductor memory and an information processing apparatus including the semiconductor memory.
New semiconductor nonvolatile memories capable of high-speed rewriting have recently been drawing attention. The nonvolatile memories utilize various materials capable of changing a state at high speed with low voltage and retaining the state spontaneously.
A typical example of the nonvolatile memories is a ferroelectric memory. A cell structure and operation of a currently mainstream ferroelectric memory are proposed in U.S. Pat. No. 4,873,664 of Patent Literature 1.
FIG. 1 illustrates an example of a method of realizing the ferroelectric memory. In this example, a memory cell is formed by one access transistor and one ferroelectric capacitor, and 1 bit is stored by complementarily writing data to a pair of memory cells, for example.
The example shown in FIG. 1 has memory cells MC11, MC21, MC31, MC41, MC12, MC22, MC32, and MC42 formed as a memory array. Each of the memory cells MC includes an access transistor and a ferroelectric capacitor. For example, the memory cell MC11 includes an access transistor T11 and a ferroelectric capacitor C11. The memory cell MC21 includes an access transistor T21 and a ferroelectric capacitor C21.
A word line decoder/driver 1 applies a voltage to a word line WL (WL1, WL2 . . . ) according to an address to be accessed.
The word line WL1 is connected with a gate electrode of each access transistor (T11, T12 . . . ) of a memory cell row including the memory cells MC11, MC21, MC31, and MC41.
The word line WL2 is connected with a gate electrode of each access transistor of a memory cell row including the memory cells MC12, MC22, MC32, and MC42.
Bit lines BL (BL1, BL2 . . . ) are arranged in a direction orthogonal to the word lines WL.
The bit lines BL1 and BL2, for example, are a bit line pair to which voltage is applied by a sense amplifier 3-1 and whose potential is detected by the sense amplifier 3-1. The bit lines BL3 and BL4 are a bit line pair to which voltage is applied by a sense amplifier 3-2 and whose potential is detected by the sense amplifier 3-2.
A plate line decoder/driver 2 applies a predetermined voltage to a plate line PL (PL1, PL2.) The plate line PL1 is connected with one terminal of each ferroelectric capacitor (C11, C21 . . . ) of the memory cell row including the memory cells MC11, MC21, MC31, and MC41.
The plate line PL2 is connected with one terminal of each ferroelectric capacitor of the memory cell row including the memory cells MC12, MC22, MC32, and MC42.
In each memory cell MC, the access transistor is turned on by the word line WL, whereby the memory cell MC is connected to the corresponding bit line BL.
In such a configuration, two ferroelectric capacitors are used to store 1 bit complementarily. Specifically, the ferroelectric capacitors C11 and C21 forming memory units MU11 and MU21 connected to the pair of bit lines BL1 and BL2 constitute a pair, and complementarily store data of 1 bit each by direction of polarization of the ferroelectric capacitors C11 and C21.
When “1” is to be written to the capacitor C11, for example, the word line WL1 is selected, the plate line PL1 is set to 0 V, and the bit lines BL1 and BL2 are driven to apply a voltage for providing a polarization direction of “1” to the capacitor C11. On the other hand, the capacitor C21 is made to have a polarization direction of “0.”
At the time of reading, when the word line WL1 is selected and the plate line PL1 is driven, charge is discharged as complementary data from the capacitors C11 and C21 into the bit line pair BL1 and BL2. A potential difference caused by this is detected by the differential type sense amplifier 3-1, whereby data can be read.
States at the time of reading will be described with reference to a hysteresis loop of FIG. 2. An axis of abscissas indicates voltage applied to ferroelectric capacitors, and an axis of ordinates indicates amount of polarization.
In an initial state of reading, the plate line PL1 and the bit line pair BL1 and BL2 are equalized to 0V, and the bit lines BL1 and BL2 are in a floating state. The capacitors C11 and C21 forming a pair are polarized in directions opposite to each other. For example, the capacitor C11 is in an (H0) state, and the capacitor C21 is in an (H1) state in FIG. 2.
A pulse of voltage Vcc is applied to the plate line PL1, whereby substantially Vcc is applied to both the capacitors C11 and C21. Both the capacitors C11 and C21 are shifted to an (H2) state. Accordingly a signal difference corresponding to a difference in amount of polarization change from the initial state occurs between the bit lines BL1 and BL2.
That is, of the capacitors C11 and C21, only the capacitor C21 causes polarization inversion, and a signal difference corresponding to the inversion appears between the bit lines BL1 and BL2. Specifically, a potential of the bit line BL2 on a side where the polarization inversion occurred is increased. The signal difference is sensed by the differential sense amplifier 3-1, whereby data is obtained.
Further, the sense amplifier 3-1 is activated to amplify the voltage of the bit line BL1 to 0 V and the voltage of the bit line BL2 to the voltage Vcc.
At this time, while the capacitor C11 remains around (H2), zero voltage is applied to the capacitor C21, and the capacitor C21 is shifted to the (H0) state.
Next, the plate line PL1 is driven to 0 V again, whereby the voltages applied to the capacitors C11 and C21 are changed to zero and (−Vcc), respectively. At this time, the capacitor C11 returns to the (H0) state, while the capacitor C21 is shifted to an (H3) state, thus inverting the direction of polarization again. Finally, when the bit lines BL1 and BL2 are returned to 0 V, the capacitors C11 and C21 are restored to the (H0) state and the (H1) state, respectively. That is, data rewriting or refresh is performed.
Since the polarization of such ferroelectric film has a spontaneous state retention capability, the ferroelectric film continues storing data without power supply as long as opposed electrodes sandwiching the ferroelectric film are maintained at the same potential.
In addition, the above-mentioned polarization inversion can be performed in a short time of a few nanoseconds with an applied voltage of 3 V or lower. Thus, unlike flash memories, the ferroelectric memory does not require a large amount of time or current consumption for data writing.
Such a semiconductor memory is expected to be used for the following applications.
A main memory of many portable electronic apparatus, for example portable telephones and PDAs is now formed by a DRAM. In these apparatus, user data and applications are stored left extracted in the DRAM so as to be used immediately on turning on power. That is, data in the DRAM is retained even at a time of nonuse of the apparatus.
However, DRAM is volatile and is therefore not able to retain data spontaneously. Thus, in order to retain the data, current needs to be sent to a memory cell array at all times even during standby, and further a refresh operation needs to be performed at a high frequency. Therefore, even while not used, the apparatus consumes a few mW of current during the standby, thus requiring frequent battery change and extra battery cost.
In addition to the problem of such battery backup, there has recently been a movement spreading to reduce power consumption during standby of electric apparatus in general in consideration for the environment. Therefore, the current consumption for data retention during standby of a DRAM included in such household electric appliances is becoming a serious problem.
When a ferroelectric memory is used as a substitute for the DRAM, the current consumption during standby of the memory can be reduced to zero while maintaining access performance similar to that of the DRAM. Alternatively, when data extracted in the DRAM is transferred at high speed and stored in a high-speed storage formed by a ferroelectric memory, the current consumption during standby can be reduced to zero by stopping refresh of the DRAM.
Incidentally, while principles of a memory (FeRAM) using ferroelectric film have been described above, MRAM, which uses magnetic tunnel film and stores data by direction of magnetization of the magnetic film, OUM, which stores data by crystal state of chalcogenide film, and the like are proposed as memory capable of writing at high speed with low voltage and spontaneously retaining data as with the ferroelectric memory.
Memories that write data at high speed with low voltage and store data spontaneously as described above, such for example as FeRAM using ferroelectric film, MRAM using magnetic tunnel film, and OUM using chalcogenide film will hereinafter be referred to as a “high-speed nonvolatile memory.”
Ideally, such a “high-speed nonvolatile memory” is capable of storing data spontaneously over a long period of time. The ability to write at high speed with low voltage, on the other hand, means a low energy barrier between different pieces of data. Therefore, the data retention of the high-speed nonvolatile memory is not so easy as that of a flash memory. For example, a small defect in film caused in a manufacturing process makes a retention period by far shorter than an ideal retention period. Nonvolatile memories generally ensure data retention for 10 years at 80° C. If the retention period is one day, a loss of data occurs in the memory, thus rendering the memory unusable.
Because of such a situation, it is very difficult to secure reliability of high-speed nonvolatile memories. An operating margin larger than necessary is generally included in design of high-speed nonvolatile memories to provide for degradation during data retention. A ferroelectric memory, for example, has a capacitor size twice or more larger than is necessary for normal sensing. Such a condition considerably hinders progress toward higher integration and increases bit cost.
As a measure against degradation during data retention of such a nonvolatile memory, refresh is considered.
For example, Japanese Patent Laid-open No. Hei 9-326200 of Patent Literature 2, though having a different object because of its assumption that a state of polarization of ferroelectric film remains, proposes periodic refresh during operation as a measure against a problem specific to a FET type ferroelectric memory (data cannot be obtained by normal reading after passage of time). Japanese Patent Laid-open No. Hei 9-326200 also proposes a startup mechanism that performs refresh at a time of turning on power by reading all data stored from polarization states by a special reading method and rewriting the data.
Japanese Patent Laid-open No. 2000-11665 of Patent Literature 3 and Japanese Patent Laid-open No. Hei 11-162182 of Patent Literature 4 propose refresh operation based on an external command. Japanese Patent Laid-open No. Hei 5-62469 of Patent Literature 5 proposes refresh based on an event signal of an internal access counter and refresh based on an event signal from a CPU processor.
However, these examples all suppose refresh during operation of the apparatus, and assume that at least the apparatus is under complete operation control of a CPU. Therefore, the examples do not suppose long-term data retention during nonuse of the apparatus. Even as for refresh at a time of turning on power, frequency of a user turning on the apparatus cannot be guaranteed nor be forced. This method is very unreliable from a viewpoint of data retention during nonuse of the apparatus, and therefore cannot ensure long-term data retention.
Furthermore, in a ferroelectric memory, the same data stored over a long period of time causes internal movable charge to be redistributed and fixed so as to cancel an internal electric field attendant on polarization, causing a shift or distortion of the hysteresis loop. This is referred to as an “imprint,” which in a bad case causes erroneous reading or erroneous writing.
The hysteresis shift caused by the movable charge is corrected by inverting data. Thus, mainly to deal with this problem, the refresh operation described in Japanese Patent Laid-open No. 2000-11665 of Patent Literature 3 performs data reading, inverted writing, and normal writing on the basis of an external command. A refresh event described in the literature occurs when a predetermined time has passed since normal writing, when power to the apparatus is turned on, or when the power to the apparatus is stopped.
During nonuse of the apparatus in this case, however, data is left as it is over an indefinite long period of time, so that a degree of deterioration of an imprint cannot be guaranteed. That is, it is not possible to perfectly prevent the state of the imprint from deteriorating to such a degree as to cause erroneous reading. Further, in that case, data is no longer restored even when refresh is performed because the data is lost at the time of reading.
Further, the sequence described above requires writing after inverting bit line data once outputted to a sense amplifier, and then rewriting after inverting the inverted bit line data. This procedure is very complex and time-consuming. Besides, when bit lines having a heavy capacitive load are inverted in the whole array, erroneous operation tends to be caused by occurrence of noise or the like.
Of course, this example is similar to the above examples in that it cannot be a sufficient measure against data retention degradation.